As electronic circuits and devices have become more complex, testing of these devices has become increasingly difficult. Test standards have been developed to address at least some of these testing difficulties. One such standard, written by the Joint Test Action Group (“JTAG”), is IEEE standard number 1149.1, which describes the Standard Test Access Port and Boundary-Scan Architecture. Boundary scan is a methodology that allows controllability and observability of the boundary pins in a JTAG-compatible device via software control. This capability allows testing of circuit boards that otherwise might not be practical or possible given the trace pitch and multi-layering of printed circuit boards today.
Typically, JTAG-compatible devices (e.g., chips, circuit boards) are connected in series in a scan chain. However, it may be desirable to connect such devices in a parallel (star) configuration for testing purposes. Performing JTAG testing on devices in a star configuration is problematic in the JTAG standard.